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IFIP WG1.3 Foundations of System Specification


Talk "Multicore Scheduling for Large Safety-Critical Applications"

by Peter Ölveczky

Fri, 11 September 2026 at 08:08 pm in Pisa, Italy

Joint work with: José Meseguer

Abstract: The single-core equivalence (SCE) technology provides the robust partitioning of multicore processors needed for estimating worst-case executing times (WCETs) and for FAA certification, which requires that change or failure of lower-criticality software does not affect higher-criticality software. However, SCE only allows running an application in a single core, and therefore cannot deal with emerging large safety-critical applications that do not fit in a single core. In this talk I introduce the "physically multicore, logically single-core" (PMLS) technology that extends SCE to such large applications which cannot be executed in a single core. The idea is to use well-known single-core methods, such as the single-core priority ceiling protocol (PCP), for task synchronization. In the accomapnying paper we study schedulability properties of PMLS, formalize PMLS executions in Maude, and use model checking to find a task allocation that makes the large application schedulable (if one exists).

Paper